1. Field of the Invention
This invention relates to the field of computer architecture. Specifically, the field of the invention is that of memory controllers used by a central processing unit for accessing system memory.
2. Prior Art
An important component in most any computer system is a means for controlling access to system memory. Since system memory holds the data and instructions used by a central processing unit (CPU), control and data transfers occur frequently between the CPU and memory. It is therefore critical to the operation of the computer system that the interface between the CPU and memory be designed in the most efficient manner possible. Many prior art systems employ a memory controller for handling the various requests for memory access made by the CPU. The use of a memory controller has been found to be particularly useful for the control of dynamic random access memory (DRAM). DRAM's require a cyclic refresh signal supplied by the computer system in order to prevent the information stored in DRAM from being destroyed. It is convenient to have a DRAM memory controller handle this refresh task thereby allowing the CPU to be fully dedicated to the task of information processing.
Memory controllers have also been found to be very useful in the prior art for handling memory access requests from the CPU for various size portions of memory. For example, the CPU may request access to a single byte (8 bits) of memory, a word (16 bits), a double word (32 bits), or a burst of data comprising multiple words. For each of these various modes of memory access, the memory controller is responsible for accepting a memory address and various control signals from the CPU, reading or writing the requested data to/from memory and generating the appropriate control signals for the CPU.
Memory controllers also provide an efficient means for handling a variety of different memory configurations without having to modify the CPU or the memory addressing scheme. For example, a particular computer system may configure memory (DRAM) as a single bank of multiple word storage or multiple banks of single word storage. The row and column dimensions of a particular memory configuration may be tailored to optimize the memory access timing for a specific application.
In order to carry out these functions, the operation of the memory controller must be synchronized in some way with the operation of the CPU. In the prior art, two methods are generally used for synchronizing the operation of the memory controller with the operation of the CPU. The first method involves the connection of the CPU clock or a derivative of it to the memory controller as part of the interface for communication between the two devices. With this method, the memory controller is required to operate synchronously with respect to the CPU. Since this method requires synchronous operation between the memory controller and the CPU, the memory controller must be designed for all CPU clock frequencies that it may support. As a result, the memory controller must be modified each time the speed of the CPU is increased even though the speed of memory may not have changed. In addition to the frequent modification of the synchronous memory controller, synchronous operation also has the disadvantage of requiring the CPU clock signal line or lines to be routed over a longer physical distance on the circuit board containing the CPU and the memory controller. As the CPU clock signal gets higher in frequency, clock loading and routing length become more crucial in the control of clock skew and EMI emissions. In a modular design where the memory controller may be on a separate circuit board, the CPU clock signal line or lines will be required to cross the connector between the circuit boards. This configuration can further add to the clock loading and routing length problems.
A second prior art method for synchronizing the operation of the memory controller and the CPU involves separate clocks for the CPU and the memory controller. Thus, since the CPU and the memory controller operate using two separate clock frequencies, the memory controller can operate asynchronously with respect to the CPU. However, these prior art systems require synchronization circuitry at the control signal interface between the memory controller and the CPU. This synchronization circuitry is required to convert from the time domain of one device to the time domain of the other. Thus, when information or control is transferred between the CPU and memory controller, the two independently clocked devices are brought into synchronization for the purposes of the control or information transfer. This prior art method however, produces a performance loss in the operation of the overall system since additional time is required for converting the control signals from the frequency of one time domain to the other.
Thus, an improved memory controller and synchronization technique is needed for overcoming the problems experienced in the prior art.